The present invention is directed to performance analysis and verification of full-chip designs.
Performance analysis/verification is an aspect of integrated circuit design in which a model of the integrated circuit is tested to determine whether it meets specified performance criteria.
Performance analysis/verification of an integrated circuit chip model may be performed in a hierarchical manner. For example, during a first pass, individual cells of the integrated circuit may be tested against desired performance goals for the individual cells. For subsequent passes, testing may then proceed at the block level and finally, at the full chip level, to determine if the overall chip meets desired performance criteria.